DRAMs are the memory of choice for many computer memory systems. In most DRAMs, single-bit storage elements or cells are arranged in an array fashion. The array is composed of rows and columns, where rows are referred to as "word lines" and columns are referred to as "bit lines". Data lines transfer data to and from the storage arrays. During conventional read and write operations, one memory cell in each column is connected to its corresponding bit line. A sense amplifier attached to each bit line amplifies and restores the signals placed on the bit line during a read operation. In a DRAM chip, read and write operations each require two steps. The first step is to select a row, which is done by asserting a row address strobe (RAS) while the desired row address is on the address inputs. An on-chip row decoder then produces a vector whose bits are zero everywhere except for a one at a selected row. This bit vector determines which row of storage cells is connected to the bit lines and their associated sense amplifiers.
The second step is to select the column, which is done by asserting a column address strobe (CAS) and a read-write signal while the desired column address is on the address inputs. The column address selects a bit from the active row of memory in each array. The selected bits are either buffered for output (during read operations) or set to values received from the data inputs (during write operations).
A VRAM is a particular type of DRAM designed specifically to allow video scanout to be independent of other frame-buffer operations in a video display system. A VRAM chip is similar to a conventional DRAM chip but contains a parallel-in/serial-out data register connected to a second data port. The serial register can be as wide as the memory array and can be parallel loaded by asserting the transfer signal while a row of memory is being read. The serial register has its own data clock, enabling it to transfer data out of the chip at high speeds. The serial register and port effectively provide a second, serial port to the memory array. If this port is used for video scanout, scanout can occur asynchronously to normal reads from and writes to the chip, virtually eliminating any video scanout problem.
One approach to enhancing performance of a DRAM or VRAM is to incorporate a block write feature into the memory circuit. A block write feature allows data to be simultaneously written to a set of bit lines along an accessed word line. In the existing art, a block write function is accomplished by accessing the word lines for a normal read, writing the data to selected bit lines by overpowering the associated sense amplifiers, and then carrying out the normal restore cycle. The problem with the approach is that the write drivers cannot "overpower" more than eight or so active sense amplifiers. Expanding beyond an eight bit line overwrite with this "brute force" approach is technologically not feasible.
The technique described herein is to momentarily turn off the clamping applied to the sense amplifiers in order to block write data onto greater than eight bit line pairs. By turning the sense amplifiers off, the write drivers can block write data onto a significantly larger number of bit lines. The problem with momentarily disconnecting the sense amps, however, is that as the sense amplifiers are floated, data on unselected bit lines may be corrupted. This is because while unaccessed bit lines are left unlatched, voltage loss, etc., is possible.
Thus, the invention described herein allows block overwriting of new data onto a significantly greater number of bit lines, without floating accessed data appearing on unselected bit lines.